The exemplary embodiments described herein relate generally to semiconductor device processing and, more specifically, to methods for the inspection and analysis of semiconductor device layouts to generate semiconductor wafers having optimized designs.
Wafers of thin slices of semiconductor materials are used as substrates for microelectronic devices in the fabrication of integrated circuits. During the fabrication of such integrated circuits, the wafers may be subjected to various processing steps such as lithography, etching, ion implantation, and deposition of various materials to form the devices. The devices are arranged in patterns in efforts to take full advantage of spacing on the wafer. The finished product (devices on wafer) is an integrated circuit (IC) chip.
The area encompassing the patterns of the devices within the chip on the wafer define care areas, which are subject to inspection in order to detect defects (missing material, extra material, and pinholes) that may affect the operability of apparatuses into which the wafers are incorporated. The care areas are marker shapes or polygons within a particular space. The marker shapes that define a care area layout design contain polygons that are arranged to selectively target a particular pattern design of the device.
Process limited yield (PLY) is a function of the sensitivity of the wafer defect inspection process. The sensitivity of the wafer defect inspection process for a given set of device patterns and the variation of designs within the device are limited by wafer defect detection noise from the care area. Each care area group is uniquely optimized for signal/noise so that background noise from the care area is minimized. Discrimination with regard to the patterning/spacing of devices of interest from the background patterning (by optimized care area markers) allows for the sensitivity in the detection of defects, which in turn affects the PLY.
Current methodologies for the generation of care areas to be used for defect inspection generally only address a low percentage of the area of a chip and are limited to pre-selecting the devices themselves or pre-designated repeating patterns of devices. In particular, the devices and patterns are preselected for inspection, and any test scripting is generally crafted specifically to such preselected devices and patterns.